A Dynamic Random Access Memory (DRAM) cell typically has a transfer device and a capacitor. The DRAM cell is so named because it can retain information only temporarily, having a retention time on the order of milliseconds, even with power continuously applied. Therefore, the cell must be read and must be refreshed at periodic intervals. Although the storage or retention time may at first appear very short, it is actually long enough to permit many memory operations between refresh cycles. The advantages of cost per bit, device density, and flexibility of use (i.e., both read and write operations are possible) have made DRAM cells the most widely used form of semiconductor memory to date.
Generally, the integrated circuit technology of a DRAM cell is based on the ability to form numerous transfer devices in a single silicon substrate. One type of transfer device is a field effect transistor (FET). There are two major types of FET: the metal-oxide-semiconductor field effect transistor or MOSFET (also called an insulated-gate FET, or IGFET), and the junction-gate field effect transistor or JFET.
A FET has a control gate, and source and drain regions formed in a substrate. The source and drain regions are conventionally formed by implanting dopant ions, such as boron, into a surface of the semiconductor substrate. The semiconductor substrate is typically made of a monocrystalline silicon containing a heavily doped p+ shallow well which is formed by ion implantation. The control gate is formed above a dielectric insulator that is deposited over the area between the source and drain regions. As voltage is applied to the control gate, mobile charged particles in the substrate form a conduction channel in the region between the source and drain regions. Thus, in a FET, a channel is induced in the surface of the silicon region between source and drain regions, and the tunneling of charges in the channel between the source and drain is controlled by a gate disposed atop the channel. Once the channel forms, the transistor turns "on" and current may flow between the source and drain regions.
The number of integrated circuits fabricated on a wafer has dramatically increased year by year. It is known that the size of each integrated circuit chip can be successfully minimized by improving the technique of integrated circuit fabrication. One method is to shorten the length of the channel in an FET. Unfortunately, shorter channels in an FET have serious drawbacks. One such drawback is the need to suppress junction leakage between the shallow well and both the source and drain. Junction leakage results in reduced retention time. The control of junction leakage becomes even more difficult as channel lengths are reduced in DRAM cells. Furthermore, future generation DRAM products will likely require lower power and fewer refresh cycles.
An important structural component used in the process of manufacturing integrated circuits is a conformal barrier or liner film. The interface between the substrate upon which the barrier film is deposited and the barrier film, at least in part, defines the isolation and dielectric characteristics of the devices utilizing the barrier film. The continuing increase in semiconductor device density has reduced the size of devices and increased their aspect ratios, making it more difficult to deposit a barrier film with the requisite conformality. In addition, it is critical that film deposition be achieved within the thermal budget. The barrier film deposition step in the manufacturing process must also minimize current leakage, which results in reduced retention time for the device.
Typically, conformal barrier films are deposited by chemical vapor deposition (CVD). CVD is a process for depositing a thin film of material onto a substrate by reacting the constituent elements from the gaseous phase on the solid surface. More specifically, a decomposable volatile compound, known as the precursor, contacts a substrate that has been heated to a temperature above which a coating or film forms on the surface of the substrate. A reactant gas may also be used in combination with the precursor.
In the low pressure chemical vapor deposition (LPCVD) of silicon nitride, a common barrier material, a chemical reaction takes place at fairly high temperatures and low pressures between ammonia (NH.sub.3) and either dichlorosilane (SiH.sub.2 Cl.sub.2) or silane (SiH.sub.4). The ratio of ammonia to dichlorosilane or silane is typically 5:1 to 10:1. The silicon-to-nitrogen ratios in such films are ideally 0.7. Although LPCVD can produce silicon nitride films with excellent conformality, the temperature at which LPCVD is conventionally conducted, 720.degree. C. to 800.degree. C., makes a satisfactory but undesirable addition to the thermal budget.
In additional to LPCVD, the nitride barrier can also be deposited using plasma enhanced chemical vapor deposition (PECVD) at about 400.degree. C. This relatively low temperature is well within the thermal budget. One significant problem with the conventional PECVD process, however, is that the barrier film produced by the process exhibits poor conformality and is thus susceptible to failure during reactive ion etching (RIE) processes needed for form the borderless contact (CB).
To overcome the shortcomings of conventional integrated circuit fabrication processes, a new process is provided for depositing a silicon nitride barrier film. An object of the present invention is to provide an improved process that deposits a highly conformal barrier film in comparison to PECVB barriers. A related object is to minimize junction leakage, which results in reduced retention time for the device. Another object of the present invention is to achieve a barrier film that is sufficiently dense to prevent dopant diffusion during the annealing steps of the integrated circuit manufacturing process and that is stable at the annealing temperatures. It is still another object to achieve a barrier film that is sufficiently permeable to hydrogen to allow passivation of surface states and dangling bonds, thereby improving device retention time. An overriding object of the present invention is to provide a process that achieves all of these beneficial properties for the barrier film while maintaining the thermal budget sufficiently low to avoid adverse impact on the device characteristics. Yet another object is to provide a barrier film that has an etch rate similar to conventional silicon nitride and, if desired, can be tuned to achieve different etching properties compared to conventional silicon nitride.